This application claims the benefit of Korean Patent Application No. 10-2004-0090892, filed on Nov. 9, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a multi bits flash memory device using a complementary metal oxide semiconductor (CMOS) and a method of operating the same.
2. Description of the Related Art
In order to increase memory density, the sizes of memory cells can be reduced. Alternatively, memory density can be increased by increasing the number of possible states of charges in each memory cell. For example, it is reported a flash memory cell having multi floating gates that can assume 4 states and, therefore, store 2 bits simultaneously.
However, memory cells have often been embodied in two dimension-structures. Two-dimensional memory cells have, in general, a planar transistor structure in which source and drain regions are formed in a substrate, a channel is formed in a portion of the substrate between the source/drain region, and a gate is formed on the channel.
Such two-dimensional devices may be operated by two bits. For example, in a 2-dimentional planar transistor including a floating gate or a charge trap layer, both ends of the floating gate or the charge trap layer adjacent to source and drain regions are used as charge storage sites or storage nodes, thus implementing 2 bit operations. However, 2-dimentional devices are not suitable for multi-bit operation more than 3 bits in performing program, erase and read operations.
In addition, multi-level memory cells with 2-dimentional structures have been developed. Floating gates of such multi-level memory cells store charges in multi levels. In this case, in order to store more than 2 bits, for example, 4 bits, at least 24, that is, 16 charge levels are required. In a nMOSFET device, a threshold voltage Vth is expected to be about 3V at a doping concentration of about 1E+18/cm3, which can be increased as the number of the donor (Nd) increases and varies according to a doping concentration of a channel or a substrate. Therefore, a threshold voltage window (ΔVth) is expected to be 3V. Such a narrow threshold voltage window hinders the obtainment of various voltage levels of more than ten in the window range, and good program/erase and read operations.
Therefore, in order to implement more than 2 bits-operation in a memory cell, for example, 4 bits or 8 bits-operation, a new memory cell with at least two charge storage sites or storage nodes must be developed.